The present invention relates to semiconductor fabrication technology, and more particularly to, a method for polishing a semiconductor wafer by CMP technique to form a required conductive pattern on the wafer.
Wiring patterns have a narrower width as a semiconductor integrated circuit becomes smaller in size. In order to decrease wiring delay, a wiring pattern formed from copper, which has a resistance smaller than aluminum, came into use. It is difficult to dry-etch copper, so that copper patterns are formed by a Damascene process. In a Damascene process, a trench in an insulating layer is filled with copper, and unnecessary copper is removed by a CMP (Chemical Mechanical Polishing) technique to form a pre-designed copper pattern.
According to a Damascene process, an SiN layer is formed on an insulating layer. Next, another insulating layer is formed on the SiN layer. Subsequently, the insulating layer is etched to form a trench using the SiN layer as an etching stop layer. The trench is used for forming a conductive pattern. After that, a TaN layer is formed over a surface of the entire structure by a sputtering process. Then, a Cu (Copper) layer is formed over the TaN layer, which is a barrier layer, so that the trench is filled up with Cu sufficiently.
A CMP process is carried out to polish and shape the Cu layer to form a conductive wiring pattern. Such a CHEMICAL-MECHANICAL POLISHING process includes the steps of removing the top of the Cu layer; removing the top of the barrier layer and removing particles for clean up the wafer. When removing the Cu layer and barrier layer, a polishing slurry is used in the CMP process. The conventional CMP apparatus use a polishing slurry at room temperature.
According to the above-described conventional Damascene process, undesirable dishing occurs. In more detail, the Cu layer may be over polished. As a result, the Cu wiring pattern is shaped not to have an enough height.
Accordingly, an object of the present invention is to provide a method and apparatus for polishing a semiconductor wafer in which dishing of a conductive pattern is decreased.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
A method for polishing a semiconductor wafer, includes the steps of: supplying a polishing slurry between a polishing pad and a semiconductor wafer; polishing a surface of the semiconductor wafer with the polishing pad in a CMP process; and controlling the temperature of the polishing slurry to be in a range between 2xc2x0 C. to 10xc2x0 C. while the semiconductor wafer is polished.
Preferably, the polishing process comprises first and second steps, in which the temperature of the polishing slurry is controlled to be at the room temperature in the first step and is controlled to be in a range between 2xc2x0 C. to 10xc2x0 C. in the second step.